1. Field of the Invention
The present invention relates to a wafer level packaging method and, more particularly, to a wafer level packaging cap for the wafer level packaging and a fabrication method thereof.
2. Description of the Related Art
Generally, devices manufactured as a chip unit and performing certain functions are extremely vulnerable to damage from moisture, particles, and high temperature, and therefore, need to be packaged. Examples of the devices include microscopic mechanisms such as a Radio Frequency (RF) filter, RF switch and Radio Frequency Micro Electro Mechanical System (RF MEMS), and an actuator.
For the package, a top surface of a device wafer, which has a device for performing certain functions, is covered and hermetically sealed with a cap having a cavity providing a space capable of receiving the device.
The term “wafer level packaging” means that, prior to dicing the wafer with a plurality of devices into individual chips, the wafer is hermetically sealed and packed with a packaging cap formed as a wafer unit.
The device wafer includes a device substrate, a device formed on a top portion of the device substrate to perform a certain function and a plurality of device pads electrically connected with the device, and is manufactured according to a general semiconductor fabrication process.
The packaging cap comprises a cap substrate having at the bottom surface a cavity of a certain volume providing a space for receiving the device and integrally packed with the device wafer, a plurality of first metal lines formed at the bottom surface of the cap substrate to correspond to a plurality of the device pads electrically connected to the device, a plurality of second metal lines formed from the bottom surface of the cap substrate to an inner surface of the cavity to correspond to each of the first metal lines, a plurality of connection holes penetrating to the top surface of the cap substrate to correspond to each of the second metal lines, a plurality of connection parts formed in each of the plurality of the connection holes and having the bottom portion electrically connected to each of the plurality of second metal lines, and a plurality of cap pads formed at the top surface of the cap substrate and electrically connected to each of top portions of the plurality of connection parts.
Sealing lines, formed of solder, on both of the device wafer and the packaging cap are melted and bonded to complete the packaging.
The fabrication method of the above packaging cap will be explained with reference to FIGS. 1A through 1E.
First, a wafer 10 is provided to be a cap substrate of a packaging cap as shown in FIG. 1A. A cavity is formed on a bottom portion of the wafer 10 according to a certain process, and a seed metal is deposited to cover the surface of the cavity and the bottom portion of the wafer 10 to form a seed layer 11.
As shown in FIG. 1B, mask patterns are formed on a top surface, i.e., an opposite side of the side with seed layer 11, of the wafer 10, and connection holes 10a are etched according to a dry etching by using an Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) process until the wafer 10 is completely penetrated.
Then, masks, forming the pattern (not shown) of the connection holes 10a, are removed according to an ashing process, and metal is deposited by plating from the seed layer 11 of the bottom of the connection holes 10a to form connection parts 12 as shown in FIG. 1C. The heights of the plurality of connection parts 12 are not identical, and therefore, the heights become identical and are cleaned according to a lapping and Chemical Mechanical Polishing (CMP) process.
Then, metal is deposited on the top surface of the wafer 10 and patterned according to a photolithography to form cap pads 13 electrically connected with the connection parts 12 as shown in FIG. 1D.
The seed layer of the bottom surface of the wafer 10 is patterned according to a photolithography to form first metal lines 11′ (refer to FIG. 1D). On the bottom surface of the wafer 10, second metal lines 14 connected to the first metal lines 11′, and sealing lines 15 are formed. The sealing lines 15 are used for packaging with the device substrate during the following packaging process.
Then, the completed packaging cap 1 is packaged with the top portion of the device wafer 2 as shown in FIG. 1E.
However, the packaging cap manufactured according to the above process has disadvantages as follows:
The wafer of the packaging cap should be manufactured to be thick in order to prevent breakage or damage of the wafer during the fabrication process. Therefore, the size of packaging cap increases.
The connection holes should be fabricated to penetrate the wafer so that it takes a long time to fabricate the packaging cap. Silicon (Si) wafer is generally used for the cap substrate; however, the silicon wafer can not have the cap substrate less than 300 μm due to the fabrication limitation thereof. Accordingly, the manufacturing cost cannot be reduced.
As described above, the connection holes are formed to penetrate the wafer. Therefore, much time is required to plate the deep connection holes with metal material so that the entire cost can increase.
The metal material is directly plated onto the connection holes formed on the cap substrate so that the metal material is not stably connected to the connection holes. Therefore, the electrical stability decreases.